Spintronics & AI Integration
Research Process
Design and fabrication of the MultiSpin.AI post-von Neumann architecture
The design and fabrication of the MultiSpin.AI post-von Neumann architecture involves a systematic process. Beginning with simulations to understand magnetic characteristics, researchers fabricate the Single-Layers Magnetic (SLMMS) using techniques like e-beam lithography, ion beam milling, and specific open processes.
Characterization and Testing of SLMMS and M2TJs
The characterization and testing phase of the MultiSpin.AI architecture involves validating the designed properties of the Single-Layer Multistate Magnetic Structures (SLMMS) and multi-level Magnetic Tunnel Junctions (M2TJs). Researchers employ simulations to analyse SLMMS magnetic properties, assessing the impact of fabrication variability on writing error and inference disturbance. Magnetic characterization includes evaluating spin-orbit torque efficiency and measuring switching speeds, with SLMMS featuring two switchable magnetic crossing ellipses (2CE) and three magnetic crossing ellipses (3CE) supporting different discrete magnetic states.
AI algorithm design, validation and specs
The integration of an n-ary cell-based crossbar architecture in the MultiSpin.AI framework presents a challenge in adapting the Multiply-Accumulate (MAC) operation algorithm due to inherent variability in the physical n-ary cells. To overcome this, error correction algorithms are under development to address variations in Magnetic Tunnel Junctions (M2TJs) within the crossbar, aiming to enhance the reliability and reproducibility of the MAC operation.
PoC demonstration
The Proof of Concept (PoC) demonstration is centred on the integration of the crossbar into a standard real-time AI computing architecture and the validation of the performance of the miniature demonstrator crossbar equipped with the multi-level spintronic cell. Collaboratively, we combine the previously fabricated 4×4 crossbar matrix of 4-level Magnetic Tunnel Junctions (M2TJs) with essential building blocks to create an efficient neuromorphic processor in the form of a miniature PCB prototype. Upon assembly and operationalization, this board serves to validate the n-ary computation capabilities.
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